- Develop and maintain System Verilog models or components within those models.
- Write test cases/compliance test cases to verify the functionality of customer DUTs and the VIP itself.
- Analyze simulation reports and debug failures in internal regressions and customer-reported issues.
- Stay updated with the latest System Verilog features , simulator simulation , and debug features.
- Stay updated with protocol-specific features (Protocol Specification updates) and develop feature enhancement plans with other team members.
- This role may require travel to the US or other locations from time to time, so strong communication skills and the ability to proactively work to resolve customer questions and issues are essential.
- Bachelor's degree in electrical or computer engineering from an accredited institution.
- Good communication skills, verbal and over email. English proficiency is required.
- Must possess excellent problem-solving and debugging skills.
- Experience in developing System Verilog / UVM-based test benches.
- Experience working with industry-standard protocols like AXI, USB, PCIe, etc.
- Strong background in functional verification fundamentals, like environment planning, test plan generation, and environment development.
- Experience using industry-standard simulation and debug tools, such as QuestaPrime , VCS , Xcellium simulators , Verdi , DVE , etc.
- Master's degree in EE or CS.
Software Engineer - San Jose, Costa Rica - Siemens Industry Software Inc. Costa Rica Branch
Descripción
Siemens EDA is a global technology leader in ElectronicDesign Automation software. Our software tools enable companies around theworld to develop highly innovative electronic products faster and morecost-effectively. Our customers use our tools to push the boundaries oftechnology and physics to deliver better products in the increasingly complexworld of chip, board, and system design.
This exciting new Verification Engineer position within theDesign Verification Technologies Group at Siemens EDA reports to the TechnicalProduct Manager for the Design Verification Technology division. In the role ofVerification Engineer, you will join a strong team that is rapidly growing itsbusiness in a fast-growing market segment
Responsibilities:
Minimum Requirements:
Preferred Qualifications :
AboutSiemens EDA Verification IP Solutions: Siemens EDA recently successfullyacquired Avery Design Systems to create the industry's most comprehensiveVerification IP solutions. Siemens EDA automates theverification and debug of complex SoCs and FPGAs, dramatically increasingproductivity and helping companies manage resources more efficiently. Itsbest-in-class technologies maximize the effectiveness of verification at theblock, subsystem, and system levels.
Siemens Software. Transform the Everyday
This position will be subject to U.S. export controlrequirements under the International Traffic in Arms Regulations (ITAR) and/orExport Administration Regulations (EAR). Employment is contingent oneither verifying the U.S. Person's status or obtaining any necessary exportlicense.
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