Velodyne Lidar

Sr. Manager ASIC Digital Design (BB-21DDE)

Encontrado en: Neuvoo Bulk CR


Velodyne Lidar provides smart, powerful lidar solutions for autonomy and driver assistance. Headquartered in San Jose, CA, Velodyne is known worldwide for its portfolio of breakthrough lidar sensor technologies. Our lidar technology has revolutionized perception and autonomy for automotive, new mobility, mapping, robotics, and security applications. We are seeking an ASIC Test & Characterization Engineer with experience in the assembly and test of complex opto-mechanical and electrical sub-systems.

Velodyne Lidar is looking for a hands-on Sr. Manager of ASIC Digital Engineering to lead and mentor a team of ASIC engineers in a fast-paced environment to complete product development deliverables and meet key business needs. In this role, you will utilize your skills to provide project leadership in the areas of digital design and FPGA integration of custom ASICs. You should have hands-on experience with complex ASIC and SOC designs for real-world product designs, as well as a proven ability to make effective decisions on how they apply to a product. You also should have a proven track record of managing engineering teams toward timely deliverables and successful project completion. 

You will be an important member of the overall R&D organization, collaborating with other disciplines of analog ASIC design, FPGA, HW and FW engineers to come up with specs for the product and implement them from RTL to GDS. This position involves close interaction with senior management and significant contributions to team growth and composition as we expand our team to meet rising demand for our products. 

Specific Job Requirements:

  • Lead and grow the ASIC digital engineering group responsible for the design, development, and implementation of new products and sustaining and enhancement of existing products.
  • Collaborate with system architects, algorithm developers, and analog designers to define solutions in early product development activities in support of next generation programs.
  • Continuously improve engineering best practices and advise team on appropriate documentation practices and use of tools.
  • Lead the execution for RTL architecture and design.
  • Responsible for verification planning, backend closure and final GDS delivery, working with other teams.
  • Support selection, contracting, and procurement of key IP, design services, and foundry partners.
  • Preferred Knowledge Requirements: 

  • Hands-on and recent experience with high speed mixed-signal digital design in FPGA & ASIC
  • Experience driving projects from inception, through architecture exploration, micro-architecture, design, tapeout and successful bring-up and qualification.
  • Experience with prototyping systems on FPGA platforms or emulators
  • Experience with using tools such as Cadence/Synopsis/Quartus for digital design and able to use virtuoso analog environment.
  • Experience with project management tools (Jira, Bitbucket, Confluence, etc.)
  • Experience with mixed-signal IP integration and development
  • Experience with both ASIC and FPGA
  • Experience in analyzing Static Timing Analysis (STA) reports, clock domain crossing, and Logical Equivalency Checks.
  • Experience with embedded processors
  • Preferred Education and Experience Requirements: 

  • BSEE, MSEE or PhD with 10+ years of relevant experience in Digital ASIC design and integration
  • 3-5 years of experience as a project lead or managing other engineers.
  • Experience with mixed-mode simulations
  • Experience with signal processing a plus.
  • Experience with automotive development processes is a plus.
  • Note to all recruitment agencies: Velodyne Lidar does not accept agency resumes. Please do not forward resumes to our career page or any Velodyne employees. Velodyne is not responsible for any fees related to any unsolicited resumes.

    calendar_todayhace 2 días

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