Intel

Structural Design RLS flow automation and library collateral enabling engineer (BB-4A6F0)

Encontrado en: Neuvoo Bulk CR

Descripción:

Job Description


GPU RLS team offers you technical career growth opportunities, inclusive work environments, a chance to work on top notch technology, access to principal engineers and highly competitive team members from which to learn from and codevelop methodologies and solutions that will directly impact Intel Corporation GPU products
Focused on enabling Intel's product roadmap, the person who joins this role, will become part of leading-edge GPU RLS team.
In this role, you can contribute in many different internal sub-scopes such as:

  • Path finding towards a robust and faster synthesis,
  • Cell placement and routing auto-convergence,
  • Ctmesh implementation and power efficiency,
  • Floor planning and library collateral installations,
  • Implement ML/AI methods and tools
  • Scan stitching through flow automation. Interface with DFX architects to implement SCAN flows to guarantee high coverage and timely design convergence along with reliable chain connectivity algorithms to detect issues and many other interesting areas.
  • The candidate should possess the below soft skills:

  • Fast learner able to follow self paced trainings
  • Effectively communicate, interact and align with business partners, team members and customers in fluent English.
  • Comfortable handling ambiguity and dynamic environments
  • Analysis of complex process issues and solution identification. Problem solving skills
  • Proactive growth mindset, self-motivated, able to work under pressure.

  • Qualifications

    You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

    Minimum Qualifications:

  • Bachelor's Degree, Licenciatura or Master's Degree in Electronic, Electrical engineering, VLSI, Computer Science or have finished all subjects and expecting graduation in less than 6 months
  • Proven experience of at least 1yr in related topics (School or previous assignment)
  • Fluency in written and spoken English (Advanced Level)
  • Experience scripting languages: Python and TCL.


  • Preferred Qualifications:

  • Experience with Synopsys suite basics: ICC, Design Compiler, Fusion Compiler, Library compiler
  • Interpret Verilog or System Verilog netlists
  • calendar_todayhace 1 día

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