Verification Engineer - Alajuela, Costa Rica - Teradyne

Descripción

Duties & Responsibilities

Digital functional verification engineer responsible for the planning, strategy, and execution of FPGA verification projects. The position requires interfacing with other functional groups (e.g. PCB, software, applications).

Required Skills/Experience

• Experience with verification planning tool to create verification plans or testplans (e.g. Cadence ePlanner)

• Experience with System Verilog and at least one functional verification methodology: UVM (preferred), OVM, or VMM

• Experience with advanced verification techniques: constrained random, feature verification, transaction level verification.

• Experience with at least one assertion language: SVA, PSL or OVL

• Expertise in testbench architecture, testbench development and Verification IP integration

• Experience with Scoreboards, reference models development and integration (e.g. SystemC, C/C++, Matlab...)

• Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)

• Experience working with revision source control (e.g. clearcase, git, svn)

• Good English language communication and documentation skills.

Desired Skills/Experience

• Experience in verification of Automated Test Equipment functionality

• Static and/or dynamic Formal Verification

• Experience with GVP source control continuous integration tool

Education

• Bachelor's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 5 years of relevant work experience